This invention relates generally to semiconductor device fabrication, and more particularly to the use of optical proximity correction (OPC) masks in such fabrication.
Since the invention of the integrated circuit (IC), semiconductor chip features have become exponentially smaller and the number of transistors per device exponentially larger. Advanced IC""s with hundreds of millions of transistors at feature sizes of 0.25 micron, 0.18 micron, and less are becoming routine. Improvement in overlay tolerances in photolithography, and the introduction of new light sources with progressively shorter wavelengths, have allowed optical steppers to significantly reduce the resolution limit for semiconductor fabrication far beyond one micron. To continue to make chip features smaller, and increase the transistor density of semiconductor devices, IC""s have begun to be manufactured that have features smaller than the lithographic wavelength.
Sub-wavelength lithography, however, places large burdens on lithographic processes. Resolution of anything smaller than a wavelength is generally quite difficult. Pattern fidelity can deteriorate dramatically in sub-wavelength lithography. The resulting semiconductor features may deviate significantly in size and shape from the ideal pattern drawn by the circuit designer. These distortions include line-width variations dependent on pattern density, which affect a device""s speed of operation, and line-end shortening, which can break connections to contacts. To avoid these and other optical proximity effects, the semiconductor industry has attempted to compensate for them in the photomasks themselves.
This compensation is generally referred to as optical proximity correction (OPC). The goal of OPC is to produce smaller features in an IC using a given equipment set by enhancing the printability of a wafer pattern. OPC applies systematic changes to mask geometries to compensate for the nonlinear distortions caused by optical diffraction and resist process effects. A mask incorporating OPC is thus a system that negates undesirable distortion effects during pattern transfer. OPC works by making small changes to the IC layout that anticipate the distortions. OPC offers basic corrections and a useful amount of device yield improvement, and enables significant savings by extending the lifetime of existing lithography equipment. Distortions that can be corrected by OPC include line-end shortening and corner rounding, among others.
Line-end shortening (LES) is the shortening of the end of a metal line end in the actual fabricated semiconductor device as compared to the circuit designer""s originally contemplated ideal device. OPC can be used to correct LES by adding serifs or hammerheads to the originally designed end in the photomask, such that during photolithography, the actually fabricated end more closely approximates the location of the originally designed end. Corner rounding is the degree to which the lithography process rounds feature corners that should be at sharp angles. OPC can be used to correct corner rounding by adding serifs to outside corners, which are called positive serifs, and subtracting serifs from the inside corners, which are called negative serifs, to the feature in the photomask.
A process window is the region enclosed on an exposure-defocus plane by two curves, corresponding to the upper and lower CD specifications, respectively. For example, FIG. 1 shows a graph 100 of a typical ED process window for a given semiconductor pattern feature. The y-axis 102 indicates exposure dose of the light source being used, whereas the x-axis 104 indicates depth of focus (DOF), which is the defocus range inside which lithographic performance is acceptable. The line 106 maps exposure dose versus DOF at one end of the tolerance range for the CD of the pattern feature, whereas the line 108 maps exposure dose versus DOF at the other end of the tolerance range for the CD of the feature.
The area 110 enclosed by the lines 106 and 108 is the ED process window for the pattern feature, indicating the ranges of both DOF and exposure dose that permit acceptable lithographic quality of the feature. Any DOF-exposure dose pair that maps within the area 110 permits acceptable lithographic quality of the pattern feature. Since the shape of the process window on the exposure-defocus plane is generally asymmetric, the CD at the process window center is not equal to the CD target. This is especially the case for isolated patterns, such as isolated trenches, even if scattering bars or anti-scattering bars are added.
Unfortunately, the process window typically varies by pattern feature. For example, the shape of the ED window for dense patterns, such as dense groupings of lines, is different than that for isolated patterns, such as isolated single lines. This is usually true even if the patterns have been modified by OPC to compensate for distortions. Individually optimizing the CD""s of a wafer""s features via OPC thus does not result in a maximized common process window over all the features. For various patterns, each having a different pitch-which is generally defined as the periodicity of a common pattern, such as a line-this means that applying OPC to each pattern to achieve identical pattern CD""s results in unequal process windows. The unequal process windows cannot be matched to one another to create a maximized common window.
Therefore, there is a need for maximizing the common process window for OPC-modified features of a semiconductor pattern over varying pitch. Such a maximization process should provide as wide a range as possible of exposure dose and DOF that will result in an acceptable lithographic image. The process should still, however, optimize the CD""s of the features as much as possible. For these and other reasons, there is a need for the present invention.
The invention relates to maximizing the common process window for optical proximity correction (OPC)-modified semiconductor features of varying pitch. For each pitch within a semiconductor design, a bias needed at the pitch that maximizes a common process window for the number of pitches given a critical dimension (CD) specification for a semiconductor design of the photomask is determined. The original layout for the semiconductor design of the photomask is then modified by performing rule-based optical-proximity correction (OPC), including adding the bias determined at each pitch, to yield a modified layout for the semiconductor design of the photomask. The modified layout is further modified by performing model-based on the modified layout such that exposed semiconductor wafer CD""s at each pitch are at least substantially equal to the CD specification for the pitch, to yield a final layout for the semiconductor design of the photomask.
The invention provides for advantages not found within the prior art. Significantly, the depth of focus (DOF) of the maximized common process window obtained by using the invention can be increased by 0.1 to 0.2 microns, as compared to the common process window achieved in accordance with the prior art. This increase in DOF means that more leeway is provided for varying DOF at various exposure doses and still yielding an acceptable lithographic image on the semiconductor wafer. This increase in DOF still achieves optimizes CD""s in accordance with the specification for the semiconductor design. Other advantages, embodiments, and aspects of the invention will become apparent by reading the detailed description that follows, and by referencing the attached drawings.